hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 132

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

of-packet.
16.6.1. Practical IRIG-106 packet word count considerations
IRIG-106 Chapter 10 stipulates a maximum allowable time interval of 100 ms for any data packet. The maximum
number of MIL-STD-1553 packet words occurs when the BC continuously transmits back-to-back 32 data word
broadcast receive with 32 data words, each with the minimal allowable intermessage gap of 4 µs, yielding 2 µs dead
time between commands. This results in repeating message transmission every 662 µs. Therefore (100 ms / 662 µs)
or 151.1 such messages occur in the maximum allowed 100 ms packet interval. Therefore, for strict compliance with
IRIG-106, the maximum number of MIL-STD-1553 words in a maximum duration 100 ms IRIG-106 packet is 151.1
messages x 33 words/message = 4,985 words.
The HI-613x permits longer packet recording times than 100 ms. The maximum contiguous RAM space in the device
RAM for an IMT Stack buffer is about 32,200 words, achievable when the device is configured as IMT only (no
concurrent BC or RTs). To achieve even larger packets, the host can accumulate Packet Body increments read from
HI-613x RAM in a separate, larger RAM. The HI-613x would probably be configured without automatic packet header
and trailer generation, to record message data in the format shown in Figure 7 “IRIG-106 Message Data Storage”
on page 67. Upon completion of each large packet (accumulated from multiple HI-613x “sub-packets”), the host
generates the packet header, channel specific data and packet trailer for the accumulated packet data body.
16.7. IMT Maximum Packet Time Register (0x002C)
This 16-bit register is read-write and is maintained by the host. This register is cleared after MR pin master reset but
is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status and Reset Register, 0x0001.
This register only applies when the monitor is configured for IRIG-106 Chapter 10 operational mode, which is
when IMT bit 0 is initialized to logic 0 in the MT Configuration Register 0x0029. In this mode, monitored message data
is stored in “data packets” in the monitor stack. The HI-613x IMT finalizes the unfinished packet if the packet data
recording time (measured in 10 µs increments) reaches the value in this register. If register value is zero, the register
is not used for determination of end-of-packet.
16.7.1. Practical IRIG-106 packet time considerations
IRIG-106 Chapter 10 stipulates a maximum packet time of 100 ms. Therefore, for strict compliance with the standard,
the maximum count contained in this register would be (100 ms / 10 µs) = 10,000 decimal. The HI-613x device logic
allows a maximum packet time greater than 100 ms. If the register contains 0xFFFF, the maximum packet time is
655.35 ms.
16.8. IMT Packet Maximum Gap Time Register (0x002D)
MSB
MSB
15 14 13 12 11 10
15 14 13 12 11 10
0
0
0
0
0
0
0
0
0
0
0
0
Register Value
Register Value
0
9
0
9
0
8
0
8
RW
RW
7
7
0
0
0
6
0
6
0
0
5
5
4
4
0
0
0
3
0
3
HOLT INTEGRATED CIRCUITS
0
0
2
2
HI-6130, HI-6131
0
1
0
1
LSB
LSB
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
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