hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 130

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

16.2. IMT Bus Monitor Address List Start Address Register (0x002F)
This 16-bit register is Read-Write and is fully maintained by the host. After MR pin master reset, this register is initialized
with 0x00B0, the default base address of the Monitor Address Table in device RAM. The host can overwrite the default
base address. This register is not affected by MT soft reset, when the MTRESET bit is asserted in the Master Status
and Reset Register, 0x0001. The Address List for IMT monitor is explained on page TBD.
16.3. IMT Bus Monitor Last Message Stack Register (0x0031)
This 16-bit register is read-only (diagram wrong) and is updated by the IMT upon completion of a monitored MIL-
STD-1553 message. This register is cleared after nMR pin master reset or by MT soft reset, when the MTRESET bit
is asserted in the Master Status and Reset Register, 0x0001. This register contains the Block Status Word address in
RAM for the last completed MIL-STD-1553 message.
16.4. IMT Bus Monitor Next Message Stack Pointer (0x0030)
This 16-bit register is read-only (diagram wrong) and is updated by the IMT after completion of a monitored MIL-
STD-1553 message. This register is cleared after nMR pin master reset or by MT soft reset, when the MTRESET bit is
asserted in the Master Status and Reset Register, 0x0001. This register contains the RAM address for the next-written
Block Status Word, for the next MIL-STD-1553 message. It mirrors the value contained in the Current Address Pointer,
word 2 in the Monitor Address List.
The IMT logic only updates this “next message address” register after message completion. Therefore, after reset, this
register does not contain a valid pointer address until the next valid message is completed. If the read value equals
zero, the “next message address” equals the stack start address.
MSB
MSB
MSB
15 14 13 12 11 10
15 14 13 12 11 10
15 14 13 12 11 10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Value
Register Value
Register Value
0
9
0
9
0
9
0
8
0
8
0
8
RW
RW
RW
7
7
7
1
0
0
0
6
0
6
0
6
1
0
0
5
5
5
4
4
4
1
0
0
0
3
0
3
0
3
HOLT INTEGRATED CIRCUITS
0
0
0
2
2
2
HI-6130, HI-6131
0
1
0
1
0
1
LSB
LSB
LSB
0
0
0
0
0
0
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
MR Reset
Host Access
Bit
130