hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 22

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

5. RAM STRUCTURES
Figure 2 shows a memory map for HI-613x memory and
registers. Application requirements dictate the specific
RAM structures needed. These structures listed here
are explained later.
5.1.
The device maintains information from the last 32
interrupts in a 64-word circular buffer in RAM known as
the Interrupt Log. Two 16-bit words characterize each
interrupt; one word identifies the interrupt type (Interrupt
Identification Word) and one word identifies the
command that generated the interrupt (Interrupt Address
Word). After reset, the Interrupt Log Address Register
contains the fixed buffer start address of 0x0180. After
each occurring interrupt, the device updates the register
to point to the log address used for the next occurring
interrupt.
5.2.
BC message sequencing uses an instruction list,
comprised of multiple 2-word entries. Each entry
consists of an instruction word (op code plus execution
condition code) followed by a parameter word. Some op
codes execute unconditionally, but most are conditional,
and execute only if the condition code specified in the
instruction word tests true. This architecture provides
flexibility for message frame scheduling and autonomous
BC program execution, based on various conditions.
5.3.
Referenced when a BC Instruction List parameter is
an address pointer, the Message Control Status Stack
consists of 8- or 16-word control blocks for individual
MIL-STD-1553 messages. Within the message control/
status block, execution parameters are provided
including inter-message gap, message format, active
bus, message command word(s), then address pointer
to a message data block in RAM (when the command
includes data) and the expected RT status response.
5.4.
When the Bus Controller executes a “subroutine call”
op code, the BC Subroutine Call Stack stores the list
address for the next op code, to be executed upon
return from subroutine. The BC call stack allows 8 levels
of nesting.
Interrupt Log Data Buffer
Bus Controller (BC) Instruction List
Bus Controller (BC) Msg Control /
Status Stack
Bus Controller (BC) Call Stack
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
22
5.5.
The Bus Controller General Purpose Queue provides a
convenient way for the BC to convey information to the
external host. Numerous BC op codes push various data
onto the queue, including time tag count, data values,
message Block Status Word or the data at specific RAM
address locations.
5.6.
The HI-613x Monitor Terminal (MT) has a 42 word
receive buffer for each bus. Received command words,
status words and data words are temporarily stored in
these buffers. At message completion, the recorded
data is copied to Monitor Terminal stack(s).
5.7.
The stack address table contains four addresses each,
for the MT command stack and MT data stack. These
addresses are: stack start address, stack end address,
current address value and a user-written address used
for generating a “stack utilization” interrupt.
5.8.
This 128-word table is optionally used to selectively
monitor MIL-STD-1553 messages based on each
command’s RT address and subaddress, and the
transmit/receive bit status.
5.9.
For applications that include a monitor terminal, the MT
operational mode uses either a single Command Stack
for recording both commands and data, or a Command
Stack plus Data Stack for segregated storage. Stack base
address and stack size are programmable. Interrupts
can be triggered at stack rollover, or at programmable
utilization levels.
5.10. RT1 and RT2 Command Illegalization
For each RT, optional illegal command detection utilizes
this table in RAM. The table can illegalize any logical
Bus Controller (BC) General
Purpose Queue
Monitor Terminal Temporary Buffers
A & B
Monitor Terminal (MT) Stack
Address Table
Monitor Terminal (MT) Message
Filter Table
Monitor Terminal (MT) Command &
Data Stacks
Tables