hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 30

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

11 − 10
Bit No.
9
8
Mnemonic
MAPSEL1:0
(HI-6130
only)
SSR8
(HI-6130
only)
MTENA
R/W
R/W
R/W
R/W
Reset
0
0
0
Function
MAP (Memory Address Pointer) Select.
This 2-bit field only applies to the HI-6131 with SPI host interface. The
host SPI relies on a hardware memory address pointer for many SPI
register or RAM accesses. This 2-bit field specifies which MAP is active
for SPI transactions:
The full 16-bit register can be directly written by the host using SPI op
code 0x10, followed by 16-bit data word. An alternative method uses SPI
op codes 0xD8 – 0xDA that write just the 2-bit MAPSEL field, without
affecting other register data. These four SPI op codes only require
transmission of an 8-bit instruction, without accompanying data.
Note: “Fast access” SPI op codes contain embedded register addresses
and use a separate memory address pointer. This preserves values
contained in MAP1 through MAP4. The “fast access MAP” cannot be
read by the host but is written each time a “fast access” op code is
processed. Fast Access op codes are provided for these SPI operations:
Single-Strobe Read for 8-Bit Parallel Bus.
This option only applies to HI-6130 devices with host parallel bus
interface configured for 8-bit bus width. When performing 2-byte memory
read accesses, some microprocessors with 8-bit bus assert separate
Read_Enable (or STROBE) pulses for high and low bytes. Other
microprocessors assert a single, wider Read_Enable (or STROBE)
pulse, while simply changing the low address bit (A0 / LB) to access the
two bytes. For this last case, the SSRD8 bit should be set when writing
device configuration, before the first register or RAM read access is
performed.
Bus Monitor Enable.
This bit is logically ANDed with the MTENA input pin. If input pin or
register bit equals logic 0, Bus Monitor operation is disabled. The
MTENA input pin should be connected to ground in applications not using
monitor mode.
When the pin and MTENA register bit are both logic 1, the Bus Monitor is
enabled, Operation commences when the receiver first decodes
MIL-STD-1553 activity meeting the “start record” criteria selected by bits
6:5 in the MT Configuration Register. If monitor operation is underway
when the MTENA register bit or input pin becomes logic 0, monitor
operation stops after completion of any message already underway;
monitor resumes when the MTENA register bit and input pin are both
logic 1.
HOLT INTEGRATED CIRCUITS
•
•
Register Bit
HI-6130, HI-6131
11-10
SPI reads to register addresses 0 through 0x000F (decimal 15)
SPI writes to register addresses 0 through 0x003F (decimal 63)
0-0
0-1
1-0
1-1
30
Active Map
MAP1
MAP2
MAP3
MAP4
MAP Register
Address
0x000B
0x000C
0x000D
0x000E
Enabling SPI
Op Code
0xDB
0xD8
0xD9
0xDA