hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 213

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

22. SERIAL EEPROM PROGRAMMING UTILITY
The HI-6130 or HI-6131 can program a serial EEPROM via the dedicated EEPROM SPI port for subsequent auto-
initialization events. The device copies host-configured registers and RAM (configuration tables and possibly data
buffers) to serial EEPROM.
Compatible SPI serial EEPROMs are 3.3V, operate in SPI modes 1 or 3 and have 128-byte pages. The serial SPI data
is clocked at 8.3 MHz SCK frequency. A 2K x 8 EEPROM can restore the lower 1K x 16 device address space. A 64K
x 8 EEPROM retains the entire 32K x 16 register/RAM address space.
22.1. Auto-Initialization
A deliberate series of events initiates copy of data from HI-6130 or HI-6131 registers and RAM to serial EEPROM.
This reduces the likelihood of accidental EEPROM overwrites. The following series of events must occur to initiate
programming:
1. Using a fresh host initialization immediately following MR master reset as the basis for EEPROM copy
2. Using the existing EEPROM configuration as the baseline for a new EEPROM configuration
3. If the application includes the Bus Controller, the BCENA input pin should be set to logic 1 now. Do not assert
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. With the AUTOEN, TXINHA and TXINHB pins in logic
0 state, apply MR master reset and wait for READY output assertion. Verify that the IRQ interrupt output does
not pulse low at READY assertion, indicating likely RT address parity error at the RTA4:0 and RTAP pins. Using
known good parameters, the host initializes device registers, the RAM descriptor table and transmit data buffers
(if necessary).
•
•
•
Skip to step 3.
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. If the application includes the Bus Controller, the BCENA
input pin should be at logic 0. With the AUTOEN pin in logic 1 state and the TXINHA and TXINHB pins in logic 0
state, apply and release MR master reset and wait for READY output assertion. Verify that the nIRQ output does
not pulse low (or go and remain low) at READY assertion. Confirm that the EECKE and RAMIF bits are logic 0
in the Operational Status Register 0x0002. If register bits 4 or 5 (RT1STEX, RT2STEX) in Master Configuration
Register 0x0000 were set by auto-initialization, reset them now. Modify register and RAM values to reflect the new
changes.
BCSTRT bit 13 in Master Configuration Register 0x0000.
If auto-initialization will be used to configure the Bus Controller, the BCENA input pin should be logic 1. The
corresponding BCENA bit 12 in Master Configuration Register 0x0000 should be logic 1, but BCSTRT register
bit 13 must remain in the post-reset logic 0 state.
If auto-initialization will be used to configure the Bus Monitor, the MTENA input pin should be logic 1. The cor-
responding MTENA bit 8 in Master Configuration Register 0x0000 should be logic 0. Until EEPROM program-
ming is complete, the terminal should be disconnected from MIL-STD-1553 buses (or other measures taken)
to prevent bus activity detection by the monitor.
If auto-initialization will be used to configure Remote Terminals RT1 and/or RT2, the RT1ENA and/or RT2ENA
input pins should be logic 1. The corresponding RT1ENA and/or RT2ENA bits 6 and 7 in Master Configura-
tion Register 0x0000 should be logic 1, but RT1STEX and RT2STEX register bits 4 and 5 must remain in the
post-reset logic 0 state.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
213