hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 224

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

While SPI command op codes are always 8 bits,
transacted addresses and register or memory data
are always 16-bit words, transferred by the SPI as two
sequential bytes. After a 2-byte read/write completion,
the active Memory Address Pointer automatically
increments to the following register address. The host
can extend the read or write operation to the next register
address by continuing to hold CE low while clocking
•
SPI Mode 0
SCK
SI
SO
CE
SPI Mode 0
SCK
SI
SO
CE
Reading MAP register 0x000E uses SPI op code
0x38
High Z
High Z
MSB
MSB
0
0
1
1
Figure 27. Single-Word (2-Byte) Read From RAM or a Register
Command Byte
Command Byte
Figure 28. Single-Word (2-Byte) Write To RAM or a Register
2
2
3
3
4
4
5
5
6
6
LSB
LSB
7
7
HOLT INTEGRATED CIRCUITS
MSB
MSB
0
0
HI-6130, HI-6131
1
1
2
Data Byte 0
2
Data Byte 0
3
3
224
4
4
SCK 16 additional times. This auto-increment feature
can be used to access one or more sequential register
addresses above the command address. Auto-increment
applies (ranging to the top of the address space) as long
as SCK continues to be clocked under continuous CE
assertion. Caution: When the primary address pointer
is used for auto-incrementing multi-word read/write and
reaches the top of the address range (0x7FFF) the next
increment rolls over the MAP value to 0x0000. The host
should avoid this situation.
5
5
6
6
LSB MSB
LSB MSB
7
7
0
0
1
1
2
Data Byte 1
2
Data Byte 1
3
3
4
4
Host may continue to assert CE
here to read sequential word(s).
Each word needs 16 SCK clocks.
Host may continue to assert CE
here to write sequential word(s).
Each word needs 16 SCK clocks.
5
5
6
6
LSB
LSB
7
7
High Z