hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 41

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

Bit No.
2 − 0
9
8
7
6
5
4
3
For the Hardware Interrupt Enable Register and the Hardware Interrupt Output Enable Register only
2
1
Mnemonic
BCTTRO
RT2TTM
RT1TTM
MTTTM
BCTTM
RT2APF
RT1APF
Reserved
RTIP
MTIP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
For the Hardware Pending Interrupt Register only
Reset
0
0
0
0
0
1
1
0
0
HOLT INTEGRATED CIRCUITS
Function
BC Time Tag Counter Rollover.
The Bus Controller time tag counter rolled over from full count to zero.
Depending on options selected in the Time Tag Configuration Register,
the BC time count may be either 16 or 32 bits.
RT2 Time Tag Match.
The 16-bit Remote Terminal 2 time tag counter incremented to a count
matching the contained value in the RT2 Time Tag Reload / Match
Register.
RT1 Time Tag Match.
The 16-bit Remote Terminal 1 time tag counter incremented to a count
matching the contained value in the RT1 Time Tag Reload / Match
Register.
MT Time Tag Match.
The Bus Monitor time tag counter incremented to a count matching the
contained value in the MT Time Tag Match Registers.
BC Time Tag Match.
The Bus Controller time tag counter incremented to a count matching
the contained value in the BC Time Tag Match Register(s).
RT2 Terminal Address Parity Fail Interrupt.
The Remote Terminal address and parity bits (latched into the RT2
Operational Status Register at rising edge of MR) do not exhibit odd par-
ity (do not have an odd number of bits having logic 1 state). Note: RT2
address parity is only checked if the RT2ENA pin is logic 1 at rising edge
of MR.
RT1 Terminal Address Parity Fail Interrupt.
The Remote Terminal address and parity bits (latched into the RT1
Operational Status Register at rising edge of MR) do not exhibit odd
parity (do not have an odd number of bits having logic 1 state). Note:
RT1 address parity is only checked if the RT1ENA pin is logic 1 at rising
edge of MR.
Bits 2-0 cannot be written and read back 000.
RT Interrupt Pending.
When this bit is high, one or more bits are set in the RT Pending
Interrupt Register. The host can read that register (0x0009) to determine
the RT1 or RT2 interrupt event(s).
MT Interrupt Pending.
When this bit is high, one or more bits are set in the MT Pending
Interrupt Register. The host can read that register (0x0008) to determine
the MT interrupt event(s).
HI-6130, HI-6131
41