hi-6131pqtf QuickLogic Corp, hi-6131pqtf Datasheet - Page 124

• Manufacturer Part Number: hi-6131pqtf
• Description: Mil-std-1553 / Mil-std-1760 3.3v Bc / Mt / Rt Multi-terminal Device
• Manufacturer: QuickLogic Corp

in Address List Word 1 by the device).
The host initializes a Monitor Address List in RAM to reserve address space for the IMT storage stack and define buffer
utilization interrupt behavior. For IMT mode, the 8-word Monitor Address List is defined as shown in Table XX.
For purposes of this discussion, it is important to make a distinction between Stack Addresses and Packet Addresses.
The Stack address range is fixed and initialized when the host writes Address List Words 0 and 2. The Packet address
range is dynamic. The Current Packet Start Address must be initialized by the host for the first data packet; however
this value is maintained by the device each time a new packet it started.
•
•
•
Words 6 − 5
Addr. List
Word 7
Word 4
Word 3
Word 2
Word 1
Word 0
Stack Start Address and Stack End Address define the Stack Start and End Address boundaries. These limits
usually do not coincide with stored data packet boundaries, except the first data packet following device MR reset
typically begins at the Stack Start Address.
Packet Start Address and Packet End Address express a smaller address range for storing an IMT data packet.
Because successive data packets are written in circular buffer fashion, there are times when Packet Start Ad-
dress approaches the Stack End Address. The packet fills the remaining stack address range and wraps around
to continue storing the packet at the Stack Start Address and beyond. In this case, Packet Start Address is
greater than Packet End Address, but both packet addresses occur between the Stack Start and End Addresses.
Current Packet Start Address is initialized by the host (typically equal to Stack Start Address) but is updated by
the device each time a data packet is finalized, and the next data packet has started at the following memory
address.
Name
Packet Fill
Warning
Interrupt
Not Used
Last Written
Block
Status Word
Address
Stack
Address
Interrupt
Stack
Address
Interrupt
Current
Packet Start
Address
Stack Start
Address
Table 13. Monitor Address List for IMT Mode
Function
These bits are not used in SMT monitor mode. They should be initialized logic 0 in
the SMT Interrupt Enable Register. These bits will always read logic 0 in the SMT
Pending Interrupt Register.
Command Stack Rollover Interrupt.
The Command Stack Pointer value (Word 1 in the SMT Address List) has rolled
over to the Command Stack Start Address (Word 0 in the SMT Address List).
Data Stack Rollover Interrupt.
The Data Stack Pointer value (Word 5 in the SMT Address List) has rolled over to
the Data Stack Start Address (Word 4 in the SMT Address List).
Command Stack Address Match Interrupt.
The Command Stack Pointer value (Word 1 in the SMT Address List) has reached
the Command Stack Address Match value in Word 3 of the SMT Address List.
Data Stack Address Match Interrupt.
The Data Stack Pointer value (Word 5 in the SMT Address List) has reached the
Data Stack Address Match value in Word 7 of the SMT Address List.
SMT Message Error Interrupt.
A non-broadcast MIL-STD-1553 message ended with an RT Status Word
containing the ME Message Error status bit set.
SMT End of Message Interrupt.
Successful completion of a MIL-STD-1553 message, regardless of validity.
HOLT INTEGRATED CIRCUITS
HI-6130, HI-6131
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