MC912DG128AMPVE Freescale Semiconductor, MC912DG128AMPVE Datasheet - Page 266

• Manufacturer Part Number: MC912DG128AMPVE
• Description: IC MCU 128K FLASH 8MHZ 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC12r

Specifications of MC912DG128AMPVE

• Core Processor: CPU12
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: HC912D
• Core: HC12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (8-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MCFLG — 16-Bit Modulus Down-Counter FLAG Register
ICPAR — Input Control Pulse Accumulators Register
Enhanced Capture Timer
Technical Data
266
RESET:
RESET:
MCZF
BIT 7
BIT 7
0
0
0
6
0
0
6
0
0
Read: any time
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
POLF3 – POLF0 — First Input Capture Polarity Status
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if
PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN
have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if
PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN
have no effect.
The flag is set when the modulus down-counter reaches $0000.
A write one to this bit clears the flag. Write zero has no effect.
Any access to the MCCNT register will clear the MCZF flag in this
register when TFFCA bit in register TSCR($86) is set.
This are read only bits. Write to these bits has no effect.
Each status bit gives the polarity of the first edge which has caused
an input capture to occur after capture latch has been read.
Each POLFx corresponds to a timer PORTx input.
Read or write any time.
Freescale Semiconductor, Inc.
For More Information On This Product,
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
5
0
0
5
0
0
Go to: www.freescale.com
Enhanced Capture Timer
4
0
0
4
0
0
PA3EN
POLF3
3
0
3
0
PA2EN
POLF2
2
0
2
0
MC68HC912DT128A — Rev 4.0
PA1EN
POLF1
1
0
1
0
PA0EN
POLF0
BIT 0
BIT 0
0
0
MOTOROLA
$00A7
$00A8