AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 1059

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43.7.4
43.7.5
43.7.5.1
43.7.5.2
43.7.5.3
1059
AT91SAM9M10
Variable Sample Rate
Power Management
Powering Down the AC-Link
Waking up the AC-link
Wake-up Triggered by the AC97 Controller
The problem of variable sample rate can be summarized by a simple example. When passing a
44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441
of them must contain valid sample data. The new AC97 standard approach calls for the addition
of “on-demand” slot request flags. The AC97 Codec examines its sample rate control register,
the state of its FIFOs, and the incoming SDATA_OUT tag bits (slot 0) of each output frame and
then determines which SLOTREQ bits to set active (low). These bits are passed from the AC97
Codec to the AC97 Controller in slot 1/SLOTREQ in every audio input frame. Each time the
AC97 controller sees one or more of the newly defined slot request flags set active (low) in a
given audio input frame, it must pass along the next PCM sample for the corresponding slot(s) in
the AC-link output frame that immediately follows.
The variable Sample Rate mode is enabled by performing the following steps:
Slot 1 of the input frame is automatically interpreted as SLOTREQ signaling bits. The AC97 Con-
troller will automatically fill the active slots according to both SLOTREQ and AC97C_OCA
register in the next transmitted frame.
The AC97 Codecs can be placed in low power mode. The application can bring AC97 Codec to
a power down state by performing sequential writes to AC97 Codec powerdown register. Both
the bit clock (clock delivered by AC97 Codec, AC97CK) and the input line (AC97RX) are held at
a logic low voltage level. This puts AC97 Codec in power down state while all its registers are
still holding current values. Without the bit clock, the AC-link is completely in a power down
state.
The AC97 Controller should not attempt to play or capture audio data until it has awakened
AC97 Codec.
To set the AC97 Codec in low power mode, the PR4 bit in the AC97 Codec powerdown register
(Codec address 0x26) must be set to 1. Then the primary Codec drives both AC97CK and
AC97RX to a low logic voltage level.
The following operations must be done to put AC97 Codec in low power mode:
At this point AC97 Codec is in low power mode.
There are two methods to bring the AC-link out of low power mode. Regardless of the method, it
is always the AC97 Controller that performs the wake-up.
The AC97 Controller can wake up the AC97 Codec by issuing either a cold or a warm reset.
• Setting the VRA bit in the AC97 Controller Mode Register (AC97C_MR).
• Enable Variable Rate mode in the AC97 Codec by performing a transfer on the Codec
• Disable Channel A clearing CEN field in the AC97C_CAMR register.
• Disable Channel B clearing CEN field in the AC97C_CBMR register.
• Write 0x2680 value in the AC97C_COTHR register.
• Poll the TXEMPTY flag in AC97C_CxSR registers for the 2 channels.
channel.
6355B–ATARM–21-Jun-10