AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 349
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AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
- Current page: 349 of 1404
- Download datasheet (22Mb)
6355B–ATARM–21-Jun-10
Note:
5. Selection of Programmable clocks
6. Enabling Peripheral Clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and
PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR
registers. Depending on the system used, 2 programmable clocks can be enabled or dis-
abled. The PMC_SCSR provides a clear indication as to which Programmable clock is
enabled. By default all Programmable clocks are disabled.
PMC_PCKx registers are used to configure programmable clocks.
The CSS and CSSMCK fields are used to select the programmable clock divider source. Five
clock options are available: main clock, slow clock, master clock, PLLACK, UPLLCK. By
default, the clock source selected is slow clock.
The PRES field is used to control the programmable clock prescaler. It is possible to choose
between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input
divided by PRES parameter. By default, the PRES parameter is set to 1 which means that
master clock is equal to slow clock.
Once the PMC_PCKx register has been programmed, The corresponding programmable
clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in
the PMC_SR register. This can be done either by polling the status register or by waiting the
interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the
PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write
operation.
If the CSS and PRES parameters are to be modified, the corresponding programmable clock
must be disabled first. The parameters can then be modified. Once this has been done, the
user must re-enable the programmable clock and wait for the PCKRDYx bit to be set.
Code Example:
Programmable clock 0 is main clock divided by 32.
Once all of the previous steps have been completed, the peripheral clocks can be enabled
and/or disabled via registers PMC_PCER and PMC_PCDR.
Depending on the system used, 19 peripheral clocks can be enabled or disabled. The
PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Code Examples:
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCK0,0x00000015)
write_register(PMC_PCER,0x00000110)
Each enabled peripheral clock corresponds to Master Clock.
AT91SAM9M10
349
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