AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 1389

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision History
6355B–ATARM–21-Jun-10
Doc. Rev
6355B
Comments
Bus Matrix
“12-layer” Matrix instead of “11-layer” in
DDRSDRC
In
- TRTP bitfield reset value (0 --> 2) changed.
- 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP: Read to Precharge”.
- TXARD (-->2), TXARDS (-->6), and TRPA (-->0) reset values changed.
In
In
Electrical Characteristics
-
- Figure below
- Ultra low power Mode value changed in
-
ERRATA
-
-
-
-
- 3
parity”
External Memories
- DQM0-DQM3 added to
-
-
- On
‘DDR2-LPDDR’ --> ‘DDRSDRC20’.
- All ‘DDR2SDRC’ changed into ‘DDRSDRC’.
Mechanical Characteristics
- New
PMC
- Note added to
Register”.
- All ‘nominal’ changed into ‘typical’.
- An empty square after letter ‘V’ removed from the
USART
- LIN Mode condition now shown in
Transmitter
VDEC
- DivX line removed from
Section 47.14 “DDRSDRC Timings”
Section 47.15.1.1 “Maximum SPI Frequency”
“Boot ROM”
“Static Memory Controller (SMC)”
“Touch Screen (TSADCC)”
“USB High Speed Host Port (UHPHS) and Device Port (UDPHS)”
Table
Section 20. “External Memories”
Section 22.7.6 “DDRSDRC Timing 2 Parameter
Section 22.7.7 “DDRSDRC Low-power
Section 22.4.4.1 “Self Refresh
“Error Corrected Code Controller (ECC)”
Figure 6-1 “AT91SAM9M10 Memory
Figure 48-1 “324-ball TFBGA Package Drawing”
,
20-5, row ‘A15’ edited.
“Unsupported ECC per 512 words”
(USART)”.
In the tables that follow, the most recent version appears first.
errata added.
Table 47-7, “Main Oscillator Characteristics,” on page 1351
Section 26.3 “Master Clock Controller”
Figure 20-4 “EBI Connections to Memory
Section 46. “Video Decoder (VDEC)”
errata added.
Mode”, UDP_EN bitfield replaced by UPD_MR.
reorganized.
Section 32. “Universal Synchronous Asynchronous Receiver
errata added.
edited.
Table 47-3, “Power Consumption for Different Modes”
Register”, UPD_MR bitfield added to the table at [21:20].
Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and
and
errata added:
Section 19. “Bus Matrix (MATRIX)”
added.
“Unsupported hardware ECC on 16-bit Nand Flash”
Register”,
“Marking”
and
and Max. weight changed in
“Uncomplete parity status when error in ECC
Section 26.11.12 “PMC Master Clock
Table.
Devices”.
errata added.
Table edited.
Table 48-2
AT91SAM9M10
Change
Request
Ref.
7171
7146
6786
7089
7134- 7193
7063
7195
7173
7148
6977
7165
7194
7192
7123
7027
6946
6954
7106
RFO
6944
6976
1389