AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 40
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AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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9.4.9
9.4.10
40
AT91SAM9M10
New ARM Instruction Set
Thumb Instruction Set Overview
Table 9-2.
.
Table 9-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Mnemonic
Mnemonic
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
SMULWy
SMLAWy
SMLAxy
SMULxy
QDADD
QDSUB
LDRBT
SMLAL
BLX
LDRH
LDRB
QADD
QSUB
LDRT
SWP
MCR
LDM
CDP
LDC
BXJ
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
(1)
ARM Instruction Mnemonic List (Continued)
New ARM Instruction Mnemonic List
Operation
Load Half Word
Load Byte
Load Register Byte with
Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Coprocessor Data Processing
Operation
Branch and exchange to Java
Branch, Link and exchange
Signed Multiply Accumulate 16 *
16 bit
Signed Multiply Accumulate Long
Signed Multiply Accumulate 32 *
16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
Mnemonic
Mnemonic
STRBT
SWPB
STRH
STRB
MRRC
MCRR
STRT
MCR2
CDP2
STRD
LDRD
MRC
BKPT
STC2
LDC2
STM
STC
PLD
CLZ
Operation
Store Half Word
Store Byte
Store Register Byte with
Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
Operation
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Move double to coprocessor
Alternative Coprocessor Data
Processing
Breakpoint
Soft Preload, Memory prepare to
load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Count Leading Zeroes
Alternative Load to Coprocessor
6355B–ATARM–21-Jun-10
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