AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 1234

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

46.8.2
Name:
Address:
Access:
• DE: Decoder Enable
0: Disables decoder.
1: Enables decoder.
Setting this bit high will start the decoding operation. Hardware will reset this bit when a picture is processed, a stream error
or ASO is detected or a bus error is received.
• ID: Interrupt Disable
0: Enables interrupts for decoder.
1: Disables interrupts for decoder.
When high, there will be no interrupts issued by the decoder. Polling must be used to see the hardware status.
• ISET: Decoder Interrupt Set
0: Clears the decoder interrupt.
Software will reset this after the interrupt is handled.
1: Sets the decoder interrupt.
This bit drives the interrupt line, OR gated with the post-processor interrupt bit. The interrupt line is not used for the decoder
if the interrupt disable bit for decoder is high.
• DR: Decoder Ready
0: Decoding in progress.
1: Decoder is ready.
When high, the hardware has decoded a picture. Hardware will self-reset.
• BE: Bus Error
0: No error.
1: A bus error has occurred.
When high, hardware has received an error response from the bus while accessing external memory. This is a fatal error
possibly caused by the incorrect allocation of decoder linear memory. Hardware will self-reset.
6355B–ATARM–21-Jun-10
ASOD
31
23
15
–
–
7
–
Decoder Interrupt Register
SBE
30
22
14
VDEC_DIR
0x00900004
Read-write
–
–
6
–
BE
29
21
13
–
–
5
–
DR
28
20
12
ID
–
–
4
27
19
11
–
–
–
3
–
TO
26
18
10
–
–
2
–
AT91SAM9M10
JPEGSD
25
17
–
9
–
1
–
ISET
ISE
DE
24
16
–
8
0
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