AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 728

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

35.9
6355B–ATARM–21-Jun-10
SD/SDIO Card Operation
The High Speed MultiMedia Card Interface allows processing of SD Memory (Secure Digital
Memory Card) and SDIO (SD Input Output) Card commands.
SD/SDIO cards are based on the Multi Media Card (MMC) format, but are physically slightly
thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental
overwriting and security features. The physical form factor, pin assignment and data transfer
protocol are forward-compatible with the High Speed MultiMedia Card with some additions. SD
slots can actually be used for more than flash memory cards. Devices that support SDIO can
use small devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth
adapters, modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cam-
eras and more.
SD/SDIO is covered by numerous patents and trademarks, and licensing is only available
through the Secure Digital Card Association.
The SD/SDIO Card communication is based on a 9-pin interface (Clock, Command, 4 x Data
and 3 x Power lines). The communication protocol is defined as a part of this specification. The
main difference between the SD/SDIO Card and the High Speed MultiMedia Card is the initial-
ization process.
5. Poll CBTC[x] bit in the DMAC_EBCISR Register.
6. If a new list of buffers shall be transferred repeat step 7. Check and handle HSMCI
7. Poll FIFOEMPTY field in the HSMCI_SR.
8. Send The STOP_TRANSMISSION command writing the HSMCI_ARG then the
9. Wait for XFRDONE in HSMCI_SR register.
h. Program LLI_W(n).DMAC_CFGx register for channel x with the following field’s
i.
j.
k. Program DMAC_DSCRx register for channel x with the address of LLI_W(0).
l.
errors.
HSMCI_CMDR.
–DST_DSCR is set to TRUE. (descriptor fetch is disabled for the DST)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero. Address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
Program LLI_W(n).DMAC_DSCRx with the address of LLI_W(n+1) descriptor. And
set the DSCRx_IF to the AHB Layer ID. This operation actually links descriptors
together. If LLI_W(n) is the last descriptor then LLI_W(n).DMAC_DSCRx points to
0.
Program DMAC_CTRLBx register for channel x with 0. its content is updated with
the LLI Fetch operation.
Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting
for request.
DMA Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
AT91SAM9M10
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