AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 234

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

234
AT91SAM9M10
An additional 200 cycles of clock are required for locking DLL
8. An Extended Mode Register set (EMRS1) cycle is issued to enable DLL. The applica-
9. Program DLL field into the Configuration Register (see
10. A Mode Register set (MRS) cycle is issued to reset DLL. The application must set
11. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
12. Two auto-refresh (CBR) cycles are provided. Program the auto refresh command
13. Program DLL field into the Configuration Register (see
14. A Mode Register set (MRS) cycle is issued to program the parameters of the DDR2-
15. Program OCD field into the Configuration Register (see
16. An Extended Mode Register set (EMRS1) cycle is issued to OCD default value. The
17. Program OCD field into the Configuration Register (see
18. An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit. The
tion must set Mode to 5 in the Mode Register (see
perform a write access to the DDR2-SDRAM to acknowledge this command. The write
address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For example,
with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address, the
DDR2-SDRAM write access should be done at the address 0x20400000.
high (Enable DLL reset).
Mode to 3 in the Mode Register (see
access to the DDR2-SDRAM to acknowledge this command. The write address must
be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should
be done at the address 0x20000000.
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command
(CBR) into the Mode Register, the application must set Mode to 4 in the Mode Register
(see
tion twice to acknowledge these commands.
low (Disable DLL reset).
SDRAM devices, in particular CAS latency, burst length and to disable DLL reset. The
application must set Mode to 3 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit
128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write
access should be done at the address 0x20000000
high (OCD calibration default).
application must set Mode to 5 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.
low (OCD calibration mode exit).
application must set Mode to 5 in the Mode Register (see
and perform a write access to the DDR2-SDRAM to acknowledge this command. The
write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. For exam-
ple, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4 banks) bank address,
the DDR2-SDRAM write access should be done at the address 0x20400000.
Section 22.7.1 on page
Section 22.7.1 on page
260). Performs a write access to any DDR2-SDRAM loca-
Section 22.7.1 on page
260). Perform a write access to any DDR2-
Section 22.7.1 on page
Section 22.7.3 on page
Section 22.7.3 on page
Section 22.7.3 on page
Section 22.7.3 on page
Section 22.7.1 on page
Section 22.7.1 on page
Section 22.7.1 on page
260) and perform a write
6355B–ATARM–21-Jun-10
260) and
262) to
262) to
262) to
262) to
260)
260)
260)