AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 774

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

36.4.10
36.4.11
36.4.12
774
AT91SAM9M10
Type ID Checking
VLAN Support
Wake-on-LAN Support
The contents of the type_id register are compared against the length/type ID of received frames
(i.e., bytes 13 and 14). Bit 22 in the receive buffer descriptor status is set if there is a match. The
reset state of this register is zero which is unlikely to match the length/type ID of any valid Ether-
net frame.
Note:
An Ethernet encoded 802.1Q VLAN tag looks like this:
Table 36-4.
The VLAN tag is inserted at the 13
the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame. The MAC can
support frame lengths up to 1536 bytes, 18 bytes more than the original Ethernet maximum
frame length of 1518 bytes. This is achieved by setting bit 8 in the network configuration register.
The following bits in the receive buffer descriptor status word give information about VLAN
tagged frames:
The receive block supports Wake-on-LAN by detecting the following events on incoming receive
frames:
If one of these events occurs Wake-on-LAN detection is indicated by asserting the wol output
pin for 64 rx_clk cycles. These events can be individually enabled through bits[19:16] of the
Wake-on-LAN register. Also, for Wake-on-LAN detection to occur, receive enable must be set in
the network control register, however a receive buffer does not have to be available. wol asser-
tion due to ARP request, specific address 1 or multicast filter events occurs even if the frame is
errored. For magic packet events, the frame must be correctly formed and error free.
A magic packet event is detected if all of the following are true:
• Bit 21 set if receive frame is VLAN tagged (i.e. type id of 0x8100)
• Bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit 20 is
• Bit 19, 18 and 17 set to priority if bit 21 is set
• Bit 16 set to CFI if bit 21 is set
• Magic packet
• ARP request to the device IP address
• Specific address 1 filter match
• Multicast hash filter match
• magic packet events are enabled through bit 16 of the Wake-on-LAN register
• the frame’s destination address matches specific address 1
• the frame is correctly formed with no errors
• the frame contains at least 6 bytes of 0xFF for synchronization
TPID (Tag Protocol Identifier) 16 bits
set bit 21 is set also.)
A type ID match does not affect whether a frame is copied to memory.
802.1Q VLAN Tag
0x8100
th
byte of the frame, adding an extra four bytes to the frame. If
First 3 bits priority, then CFI bit, last 12 bits VID
TCI (Tag Control Information) 16 bits
6355B–ATARM–21-Jun-10