AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 578

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 32-49. Slave Node Configuration, NACT = PUBLISH
Figure 32-50. Slave Node Configuration, NACT = SUBSCRIBE
Figure 32-51. Slave Node Configuration, NACT = IGNORE
32.7.8.22
6355B–ATARM–21-Jun-10
TXRDY
RXRDY
LINIDRX
US_LINID
US_RHR
LINTC
TXRDY
RXRDY
LINIDRX
US_LINID
US_RHR
LINTC
TXRDY
RXRDY
LINIDRX
US_LINID
US_THR
LINTC
Write
Read
Read
Read
Read
Read
LIN Frame Handling With The Peripheral DMA Controller
Break
Break
Break
The USART can be used in association with the Peripheral DMA Controller (PDC) in order to
transfer data directly into/from the on- and off-chip memories without any processor intervention.
Synch
Synch
Synch
– Check the LIN errors
Protected
Protected
Protected
Identifier
Identifier
Identifier
Data 1
Data 2
Data 1
Data 1
Data 1
Data 1
Data 3
Data N-2
Data N
Data N-1
Data N-1
Data N-1
Data N-1
Data N
Data N
Data N
AT91SAM9M10
Data N
Checksum
Checksum
Checksum
578