AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 48

• Manufacturer Part Number: AT91SAM9M10-CU
• Description: IC MCU 16/32BIT ARM9 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9M10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 133 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 16 bit
• Operating Supply Voltage: 1.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
• Controller Family/series: AT91
• No. Of I/o's: 160
• Ram Memory Size: 64KB
• Cpu Speed: 400MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Cpu Family: AT91
• Device Core: ARM926EJ-S
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 64KB
• # I/os (max): 160
• Number Of Timers - General Purpose: 7
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 1.1/1.95/3.6V
• Operating Supply Voltage (min): 0.9/1.65/1.8/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.8
9.8.1
9.8.2
9.8.3
48
Tightly-Coupled Memory Interface
AT91SAM9M10
TCM Description
Enabling and Disabling TCMs
TCM Mapping
The ARM926EJ-S processor features a Tightly-coupled Memory (TCM) interface, which enables
separate instruction and data TCMs (ITCM and DTCM) to be directly reached by the processor.
TCMs are used to store real-time and performance critical code, they also provide a DMA sup-
port mechanism. Unlike AHB accesses to external memories, accesses to TCMs are fast and
deterministic and do not incur bus penalties.
The user has the possibility to independently configure each TCM size with values within the fol-
lowing ranges, [0K Byte, 64K Bytes] for ITCM size and [0K Byte, 64K Bytes] for DTCM size.
TCMs can be configured by two means: HMATRIX TCM register and TCM region register (regis-
ter 9) in CP15 and both steps should be performed. HMATRIX TCM register sets TCM size
whereas TCM region register (register 9) in CP15 maps TCMs and enables them.
The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable
code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to
PC-relative literal pools.
Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register.
Then enabling TCMs is performed by using TCM region register (register 9) in CP15. The user
should use the same sizes as those put in HMATRIX TCM register. For further details and pro-
gramming tips, please refer to chapter 2.3 in ARM926EJ-S TRM.
The TCMs can be located anywhere in the memory map, with a single region available for ITCM
and a separate region available for DTCM. The TCMs are physically addressed and can be
placed anywhere in physical address space. However, the base address of a TCM must be
aligned to its size, and the DTCM and ITCM regions must not overlap. TCM mapping is per-
formed by using TCM region register (register 9) in CP15. The user should input the right
mapping address for TCMs.
6355B–ATARM–21-Jun-10