AT91SAM9M10-CU Atmel, AT91SAM9M10-CU Datasheet - Page 138
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AT91SAM9M10-CU
Manufacturer Part Number
AT91SAM9M10-CU
Description
IC MCU 16/32BIT ARM9 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9M10-CU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
133 MHz
Number Of Programmable I/os
5
Number Of Timers
2 x 16 bit
Operating Supply Voltage
1.65 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9M10-G45-EK
Controller Family/series
AT91
No. Of I/o's
160
Ram Memory Size
64KB
Cpu Speed
400MHz
No. Of Timers
2
Rohs Compliant
Yes
Cpu Family
AT91
Device Core
ARM926EJ-S
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
64KB
# I/os (max)
160
Number Of Timers - General Purpose
7
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (max)
1.1/1.95/3.6V
Operating Supply Voltage (min)
0.9/1.65/1.8/3V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Package Type
TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91SAM9M10-CU
Manufacturer:
Atmel
Quantity:
996
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19.5.2.1
19.5.2.2
6355B–ATARM–21-Jun-10
Round-Robin Arbitration
Fixed Priority Arbitration
For each slave, each master x is assigned to one of the slave priority pools through the Priority
Registers for Slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating
masters requests, this programmed priority level always takes precedence.
After reset, all the masters are belonging to the lowest priority pool (MxPR = 0) and so are
granted bus access in a true Round-Robin fashion.
The highest priority pool must be specifically reserved for masters requiring very low access
latency. If more than one master belong to this pool, these will be granted bus access in a
biased Round-Robin fashion which allow tight and deterministic maximum access latency from
AHB bus request. In fact, at worst, any currently high priority master request will be granted after
the current bus master access is ended and the other high priority pool masters, if any, have
been granted once each.
The lowest priority pool shares the remaining bus bandwidth between AHB Masters.
Intermediate priority pools allow fine priority tuning. Typically, a moderately latency critical mas-
ter or a bandwidth only critical master will use such a priority level. The higher the priority level
(MxPR value), the higher the master priority.
All combination of MxPR values are allowed for all masters and slaves. For example some mas-
ters might be assigned to the highest priority pool (round-robin) and the remaining masters to
the lowest priority pool (round-robin), with no master for intermediate fix priority levels.
If more than one master is requesting the slave bus, whatever are the respective masters priori-
ties, no master will be granted the slave bus for two consecutive runs. A master can only get
back to back grants as long as it is the only requesting master.
This arbitration algorithm is the first and only applied between masters from distinct priority
pools. It is also used inside priority pools other than the highest and lowest ones (intermediate
priority pools).
It allows the Bus Matrix arbiters to dispatch the requests from different masters to the same
slave by using the fixed priority defined by the user in the MxPR field for each master inside the
MATRIX_PRAS and MATRIX_PRBS Priority Registers. If two or more master requests are
active at the same time, the master with the highest priority number MxPR is serviced first.
Inside intermediate priority pools, if two or more master requests with the same priority are
active at the same time, the master with the highest number is serviced first.
This algorithm is only used inside the highest and lowest priority pools. It allows the Bus Matrix
arbiters to dispatch the requests from different masters to the same slave in a fair way. If two or
more master requests are active at the same time inside the priority pool, they are serviced in a
round-robin increasing master number order.
AT91SAM9M10
138
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