DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 135

MCU 3V 384K I-TEMP 100-TQFP

DF2239TF16I

Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2239TF16I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
2.4.2
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored (When an
instruction is fetched, the least significant PC bit is regarded as 0).
2.4.3
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions except for the STC instruction is executed, all interrupts including NMI
will be masked for three states after execution is completed.
Bit
7
6 to 3
2
1
0
Program Counter (PC)
Extended Control Register (EXR)
Bit Name
T
I2
I1
I0
SP (ER7)
Initial Value
0
All 1
1
1
1
Figure 2.8 Stack Status
R/W
R/W
R/W
R/W
R/W
Description
Trace Bit
When this bit is set to 1, a trace exception is
generated each time an instruction is
executed. When this bit is cleared to 0,
instructions are executed in sequence.
Reserved
These bits are always read as 1.
These bits designate the interrupt mask level
(0 to 7). For details, refer to section 5, Interrupt
Controller.
Rev. 6.00 Mar. 18, 2010 Page 73 of 982
Stack area
Free area
REJ09B0054-0600
Section 2 CPU

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