DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 626

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 15 Serial Communication Interface (SCI)
Rev. 6.00 Mar. 18, 2010 Page 564 of 982
REJ09B0054-0600
Bit
5
4
Bit Name
ORER
FER
Initial
Value
0
0
R/W
R/(W) *
R/(W) *
1
1
Description
Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
[Setting condition]
When the next serial reception is completed while
RDRF = 1
The receive data prior to the overrun error is
retained in RDR, and the data received
subsequently is lost. Also, subsequent serial
reception cannot be continued while the ORER flag
is set to 1. In clocked synchronous mode, serial
transmission cannot be continued either.
[Clearing condition]
When 0 is written to ORER after reading ORER =
1
The ORER flag is not affected and retains its
previous state when the RE bit in SCR is cleared to
0.
Framing Error
Indicates that a framing error occurred during
reception in asynchronous mode, causing
abnormal termination.
[Setting condition]
When the stop bit is 0
In 2 stop bit mode, only the first stop bit is checked
for a value to 1; the second stop bit is not checked.
If a framing error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the FER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be
continued, either.
[Clearing condition]
When 0 is written to FER after reading FER = 1
In 2-stop-bit mode, only the first stop bit is
checked.
The FER flag is not affected and retains its
previous state when the RE bit in SCR is cleared to
0.