DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 234

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 7 Bus Controller
7.3.4
BCRH selects enabling or disabling of idle cycle insertion, and the memory interface for area 0.
Rev. 6.00 Mar. 18, 2010 Page 172 of 982
REJ09B0054-0600
Bit
7
6
5
4
3
2 to
0
Bit Name
ICIS1
ICIS0
BRSTRM
BRSTS1
BRSTS0
—
Bus Control Register H (BCRH)
Initial Value R/W
1
1
0
1
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insert 1
Selects whether or not one idle cycle state is to be
inserted between bus cycles when successive external
read cycles are performed in different areas.
0: Idle cycle not inserted in case of successive external
1: Idle cycle inserted in case of successive external read
Idle Cycle Insert 0
Selects whether or not one idle cycle state is to be
inserted between bus cycles when successive external
read and write cycles are performed.
0: Idle cycle not inserted in case of successive external
1: Idle cycle inserted in case of successive external read
Burst ROM enable
Selects whether area 0 is used as a burst ROM
interface.
0: Area 0 is basic bus interface
1: Area 0 is burst ROM interface
Burst Cycle Select 1
Selects the number of burst cycles for the burst ROM
interface.
0: Burst cycle comprises 1 state
1: Burst cycle comprises 2 states
Burst Cycle Select 0
Selects the number of words that can be accessed in a
burst ROM interface burst access.
0: Max. 4 words in burst access
1: Max. 8 words in burst access
Reserved
The write value should always be 0.
read cycles in different areas
cycles in different areas
read and write cycles
and write cycles