DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 650

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 15 Serial Communication Interface (SCI)
15.4.3
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin when
setting CKE1 = 0 and CKE0 = 1. The frequency of the clock output in this case is equal to the bit
rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as
shown in figure 15.7.
Rev. 6.00 Mar. 18, 2010 Page 588 of 982
REJ09B0054-0600
SCK
TxD
Figure 15.7 Relationship between Output Clock and Transfer Data Phase
Clock
Internal basic
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Note: Example for H8S/2239 Group with the ABCS bit in SEMR_0 set to a value other than 1.
Figure 15.6 Receive Data Sampling Timing in Asynchronous Mode
When ABCS is set to 1, the clock frequency is 8 times the bit rate and sampling of received
data takes place at the fourth rising edge of the basic clock.
0
D0
0
8 clocks
D1
Start bit
D2
16 clocks
(Asynchronous Mode)
7
D3
D4
1 frame
D5
15 0
D6
D7
D0
0/1
1
7
1
15 0
D1