DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 332

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 8 DMA Controller (DMAC)
resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and
this operation is repeated until the transfer ends.
DREQ Pin Low Level Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 8.32 shows an example of single address mode transfer activated by the DREQ pin low
level.
Rev. 6.00 Mar. 18, 2010 Page 270 of 982
REJ09B0054-0600
Figure 8.32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer
Address bus
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DMA control
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of
φ
Idle
[1]
Request
Bus release
Minimum of
2 cycles
[2]
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
[4]
Request
Bus release
Minimum of
2 cycles
[5]
φ
, and the request is held.)
[6]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
[7]
release
Bus
φ
,