DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 345

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

• DTC enable registers A to G, and I (DTCERA to DTCERG, and DTCERI)
• DTC vector register (DTVECR)
9.2.1
MRA selects the DTC operating mode.
Bit
7
6
5
4
3
2
1
Bit Name
SM1
SM0
DM1
DM0
MD1
MD0
DTS
DTC Mode Register A (MRA)
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0×: SAR is fixed
10: SAR is incremented after a transfer
11: SAR is decremented after a transfer
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0×: DAR is fixed
10: DAR is incremented after a transfer
11: DAR is decremented after a transfer
DTC Mode 1 and 0
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in
repeat mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
Rev. 6.00 Mar. 18, 2010 Page 283 of 982
Section 9 Data Transfer Controller (DTC)
REJ09B0054-0600