DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 239
DF2239TF16I
Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2239TF16I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
HD64F2239TF16I
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Table 7.2
7.4.3
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode. The bus specifications described here cover basic items
only, and the sections on each memory interface (7.6, Basic Bus Interface and 7.7, Burst ROM
Interface) should be referred to for further details.
(1) Area 0: Area 0 includes on-chip ROM, and in ROM-disabled extended mode, all of area 0 is
(2) Areas 6 to 1: In external extended mode, all of areas 6 to 1 is external space. When area 6 to 1
(3) Area 7: Area 7 includes the on-chip RAM and internal l/O registers. In external extended
ABWCR
ABWn
0
1
external space. In ROM-enabled extended mode, the space excluding on-chip ROM is external
space.
When area 0 external space is accessed, the CS0 signal can be output.
Either basic bus interface or burst ROM interface can be selected for area 0.
external space is accessed, the CS6 to CS1 pin signals respectively can be output. Only the
basic bus interface can be used for areas 6 to 1.
mode, the space excluding the on-chip RAM and internal l/O registers, is external space. The
on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to
1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding
space becomes external space.
When area 7 external space is accessed, the CS7 signal can be output.
Bus Interface for Each Area
ASTCR
ASTn
0
1
0
1
Bus Specifications for Each Area (Basic Bus Interface)
WCRH, WCRL
Wn1
⎯
0
1
⎯
0
1
Wn0
⎯
0
1
0
1
⎯
0
1
0
1
Bus Width Number of Access
16
8
Bus Specifications (Basic Bus Interface)
States
2
3
2
3
Rev. 6.00 Mar. 18, 2010 Page 177 of 982
Section 7 Bus Controller
Number of Program
Wait States
0
0
1
2
3
0
0
1
2
3
REJ09B0054-0600
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