DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 620

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 15 Serial Communication Interface (SCI)
• Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Rev. 6.00 Mar. 18, 2010 Page 558 of 982
REJ09B0054-0600
Bit
7
6
5
4
Bit Name
TIE
RIE
TE
RE
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag in
SSR, then clearing it to 0, or clearing the TIE bit to
0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF, FER,
PER, or ORER flag in SSR, then clearing the flag
to 0, or clearing the RIE bit to 0.
Transmit Enable
When this bit s set to 1, transmission is enabled.
In this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0.
SMR setting must be performed to decide the
transfer format before setting the TE bit to 1. When
this bit is cleared to 0, the transmission operation is
disabled, and the TDRE flag is fixed at 1.
Receive Enable
When this bit is set to 1, reception is enabled.
Serial reception is started in this state when a start
bit is detected in asynchronous mode or serial
clock input is detected in clocked synchronous
mode.
SMR setting must be performed to decide the
reception format before setting the RE bit to 1.
Clearing the RE bit to 0 does not affect the RDRF,
FER, and ORER flags, which retain their states.