DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 338

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 8 DMA Controller (DMAC)
8.7
8.7.1
Except for forced termination of the DMAC, the operating (including transfer waiting state)
channel setting should not be changed. The operating channel setting should only be changed
when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
• DMAC control starts one cycle before the bus cycle, with output of the internal address.
Rev. 6.00 Mar. 18, 2010 Page 276 of 982
REJ09B0054-0600
DMA Internal
address
DMA register
operation
DMA control
Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 8.38 shows an
example of the update timing for DMAC registers in dual address transfer mode.
[1]
[2]
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
[3]
Note: In single address transfer mode, the update timing is the same as [1].
φ
Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Usage Notes
DMAC Register Access during Operation
Idle
[1]
Transfer
source
Read
Figure 8.38 DMAC Register Update Timing
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
[1]
Transfer
source
Read
[2']
DMA read
DMA last transfer cycle
destination
Transfer
Write
DMA write
[3]
Dead
DMA
dead
Idle