DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 552

MCU 3V 384K I-TEMP 100-TQFP

DF2239TF16I

Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2239TF16I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
(6) Data Field
The data field is a field for data transmission/reception to the slave unit. The master unit
transmits/receives data to/from the slave unit using the data field. The data field is comprised of
data bits, a parity bit, and an acknowledge bit.
The data bits include eight bits and are output MSB first.
The parity bit and acknowledge bit following the data bits are output from the master unit and
slave unit, respectively.
Broadcast communications are performed only for the transmission of the master unit. In this case,
the acknowledge bit is ignored. Operations in master transmission and master reception are
described below.
(a) Master Transmission
(b) Master Reception
Rev. 6.00 Mar. 18, 2010 Page 490 of 982
REJ09B0054-0600
The master unit transmits the data bits and parity bit to the slave unit to write data from the
master unit to the slave unit. The slave unit receives the data bits and parity bit, and returns the
acknowledgement if the parity bit is correct and the receive buffer is empty. If the parity bit is
not correct or the receive buffer is not empty, the slave unit rejects acceptance of
corresponding data and does not return the acknowledgement.
When the slave unit does not return the acknowledgement, the master unit retransmits the same
data. This operation is repeated until either the acknowledgement from the slave unit is
detected or the maximum number of data transfer bytes is exceeded.
When the parity is correct and the acknowledgement is output from the slave unit, the master
unit transmits the subsequent data if data remains and the maximum number of transfer bytes
is not exceeded.
In the case of broadcast communications, the slave unit does not return the acknowledgement,
and the master unit transfers data byte by byte.
The master unit outputs synchronous signals corresponding to all data bits to be read from the
slave unit.
The slave unit outputs the data bits and parity bit on the bus in accordance with the
synchronous signals from the master unit.
The master unit reads the parity bit output from the slave unit, and checks the parity. If the
parity is not correct, or the receive buffer is not empty, the master unit rejects acceptance of the
data, and does not return the acknowledgement. The master unit reads the same data repeatedly
if the number of data does not exceed the maximum number of transfer bytes in one frame. If
the parity is correct and the receive buffer is empty, the master unit accepts data and returns the

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