DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 333
DF2239TF16I
Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2238RFA6V.pdf
(1048 pages)
Specifications of DF2239TF16I
Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
HD64F2239TF16I
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DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
8.5.11
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table
8.11 summarizes the priority order for DMAC channels.
Table 8.11 DMAC Channel Priority Order
Short Address Mode
Channel 0A
Channel 0B
Channel 1A
Channel 1B
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for
another channel is issued during a transfer, when the bus is released, the DMAC selects the
highest-priority channel from among those issuing a request according to the priority order shown
in table 8.11. During burst transfer, or when one block is being transferred in block transfer, the
channel will not be changed until the end of the transfer. Figure 8.33 shows a transfer example in
which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
Multi-Channel Operation
Full Address Mode
Channel 0
Channel 1
Rev. 6.00 Mar. 18, 2010 Page 271 of 982
Section 8 DMA Controller (DMAC)
Priority
High
Low
REJ09B0054-0600
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