DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 556

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Table 14.5 Control Field for Locked Slave Unit
(1) Slave Status Read (Control Bits: H'0, H'6)
The master unit can decide the reason the slave unit does not return the acknowledgement (ACK)
by reading the slave status (H'0, H'6). The slave status indicates the result of the last
communications that the slave unit performs. All slave units can provide slave status information.
Figure 14.3 shows bit configuration of the slave status.
Rev. 6.00 Mar. 18, 2010 Page 494 of 982
REJ09B0054-0600
Setting
Value
H'0
H'4
H'5
Notes: 1. Since this LSI can support up to mode 2, bits 6 and 7 are fixed to 10.
Bit 3
0
0
0
2. The value of bit 4 can be selected by the STE bit in the IEBus master unit address register 1 (IEAR1).
3. The slave receive buffer is a buffer which is accessed during data write
4. The slave transmit buffer is a buffer which is accessed during data read
MSB
(control bits: H'8, H'A, H'B, H'E, H'F).
In this LSI, the slave receive buffer corresponds to the IEBus receive buffer register (IERBR);
and bit 2 is the value of the RxRDY flag in the IEBus receive status register (IERSR).
(control bits: H'3, H'7).
In this LSI, the slave transmit buffer corresponds to the IEBus transmit buffer register (IETBR)
when SRQ = 1 in the IEBus general flag register (IEFLG); and bit 1 is a value which reverses the
TxRDY flag in the IEBus transmit/runaway status register (IETSR).
Bit 7
Bit 2
0
1
1
Figure 14.3 Bit Configuration of Slave Status (SSR)
Bit
Bit 7,
bit 6
Bit 5
Bit 4 *
Bit 3
Bit 2
Bit 1 *
Bit 0 *
Bit 6
2
3
4
Bit 1
0
0
0
Value Description
Bit 5
00
01
10
11
0
0
1
0
0
1
0
1
0
1
Mode 0
Mode 1
Mode 2
For future use
Fixed 0
Slave transmission halted
Slave transmission enabled
Fixed 0
Unit is unlocked
Unit is locked
Slave receive buffer is empty
Slave receive buffer is not empty
Slave transmit buffer is empty
Slave transmit buffer is not empty
Bit 4
Bit 0
0
0
1
Bit 3
Indicates the highest mode
supported by a unit. *
Function
Reads slave status
Reads locked address (upper 8 bits)
Reads locked address (lower 4 bits)
Bit 2
Bit 1
1
Bit 0
LSB