DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 734

MCU 3V 384K I-TEMP 100-TQFP

DF2239TF16I

Manufacturer Part Number
DF2239TF16I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2239TF16I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2239TF16I
HD64F2239TF16I
Section 16 I
16.4.7
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 16.19 shows the IRIC set timing and SCL control.
Rev. 6.00 Mar. 18, 2010 Page 672 of 982
REJ09B0054-0600
IRIC Setting Timing and SCL Control
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I
(c) When FS = 1 and FSX = 1 (synchronous serial format)
2
C Bus Interface (IIC) (Option)
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
SCL
SDA
IRIC
User processing
Figure 16.19 IRIC Setting Timing and SCL Control
8
8
7
7
7
7
8
8
8
8
Write to ICDR (transmit)
or read ICDR (receive)
Clear
IRIC
Write to ICDR (transmit)
or read ICDR (receive)
Write to ICDR (transmit)
or read ICDR (receive)
9
A
A
9
2
2
C bus format, no wait)
C bus format, wait inserted)
Clear IRIC
Clear IRIC
Clear
IRIC
1
1
1
1
1
1
2
2
2
2
2
2

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