DF2239TF16I Renesas Electronics America, DF2239TF16I Datasheet - Page 502

• Manufacturer Part Number: DF2239TF16I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2239TF16I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2239TF16I; HD64F2239TF16I

Section 11 16-Bit Timer Pulse Unit (TPU)
11.10.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 11.54 shows the operation timing when there is contention between TCNT write and
overflow.
11.10.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
11.10.14 Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DMAC* or DTC activation source. Interrupts should
therefore be disabled before entering module stop mode.
Note: * Supported only by the H8S/2239 Group.
Rev. 6.00 Mar. 18, 2010 Page 440 of 982
REJ09B0054-0600
Figure 11.54 Contention between TCNT Write and Overflow
Address
Write signal
TCNT
TCFV flag
φ
H'FFFF
Prohibited
2
TCNT write cycle
state of a TCNT write cycle, when
TCNT address
T
1
T
2
M
TCNT write data