sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 104

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1
1
Port Integration Module (S12HYPIMV1)
2.3.51
2.3.52
104
Address 0x0273
DDR1AD
Address 0x0274
Read: Anytime
Write: Anytime
Read: Always reads 0x00
Write: Unimplemented
Field
Reset
Reset
7-0
W
W
R
R
DDR1AD7
Port AD data direction—
This bit determines whether the associated pin is an input or output.
To use the digital input function the ATD Digital Input Enable Register (ATDDIEN) has to be set to logic level “1”.
1 Associated pin is configured as output
0 Associated pin is configured as input
Port AD Data Direction Register (DDR1AD)
PIM Reserved Register
0
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT1AD registers, when changing the
DDR1AD register.
= Unimplemented or Reserved
DDR1AD6
Figure 2-49. Port AD Data Direction Register (DDR1AD)
0
0
0
6
6
Table 2-44. DDR1AD Register Field Descriptions
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
DDR1AD5
Figure 2-50. PIM Reserved Register
0
0
0
5
5
DDR1AD4
NOTE
0
0
0
4
4
Description
DDR1AD3
3
0
3
0
0
DDR1AD2
0
0
0
2
2
DDR1AD1
Freescale Semiconductor
Access: User read/write
0
0
0
1
1
Access: User read
DDR1AD0
0
0
0
0
0
1
1