sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 185

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

6.1.4
The DBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU monitoring is disabled. When
the CPU enters active BDM Mode through a BACKGROUND command, the DBG module, if already
armed, remains armed.
The DBG module tracing is disabled if the MCU is secure, however, breakpoints can still be generated
6.1.5
6.2
There are no external signals associated with this module.
Freescale Semiconductor
Enable
BDM
x
0
0
1
1
TAGHITS
SECURE
CPU BUS
— Begin and End alignment of tracing to trigger
READ TRACE DATA (DBG READ DATA BUS)
External Signal Description
Modes of Operation
Block Diagram
Active
BDM
x
0
1
0
1
Secure
MCU
1
0
0
0
0
Table 6-2. Mode Dependent Restriction Summary
COMPARATOR A
COMPARATOR C
COMPARATOR B
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 6-1. Debug Module Block Diagram
Matches Enabled
Comparator
Yes
Yes
Yes
No
MATCH1
MATCH0
MATCH2
Active BDM not possible when not enabled
Breakpoints
Only SWI
Possible
Yes
Yes
No
CONTROL
MATCH
LOGIC
TAG &
TRANSITION
STATE
BREAKPOINT REQUESTS
Possible
Tagging
S12S Debug Module (S12SDBGV2)
Yes
Yes
Yes
No
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
STATE
TRACE
CONTROL
TRIGGER
Possible
Tracing
Yes
Yes
No
No
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