sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 267

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Several examples of PLL divider settings are shown in
optimum stability and shortest lock time:
The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with
the reference clock (REFCLK = IRC1M or OSCCLK/REFDIV+1)). Correction pulses are generated based
on the phase difference between the two signals. The loop filter alters the DC voltage on the internal filter
capacitor, based on the width and direction of the correction pulse, which leads to a higher or lower VCO
frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the
VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance
check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously
(during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK
will have stabilized to the programmed frequency.
Freescale Semiconductor
4MHz
f
osc
off
off
off
•
•
•
•
•
Use lowest possible f
Use highest possible REFCLK frequency f
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within the tolerance
the VCO frequency is out of the tolerance
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
REFDIV[3:0]
$00
$00
$00
$00
1MHz
1MHz
1MHz
4MHz
f
REF
REFFRQ[1:0] SYNDIV[5:0]
VCO
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 7-23. Examples of PLL Divider Settings
00
00
00
01
/ f
REF
ratio (SYNDIV value).
$1F
$1F
$0F
$03
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
REF
unl
64MHz
64MHz
32MHz
32MHz
.
.
f
Table
VCO
7-23. The following rules help to achieve
VCOFRQ[1:0] POSTDIV[4:0]
01
01
00
01
Lock
$03
$00
$00
$00
and is cleared when
16MHz
64MHz
32MHz
32MHz
f
PLL
32MHz
16MHz
16MHz
8MHz
f
bus
267