sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 124

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Port Integration Module (S12HYPIMV1)
124
DDRV
DDRV
DDRV
DDRV
DDRV
DDRV
Field
7
6
5
4
3
2
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output or enable the TIM1 channel 3 output compare function, it will force the I/O
state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output or enable the TIM1 channel 2 output compare function, it will force the I/O
state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if IIC is routing to PV and IIC is enabled, it will force the I/O state to be open drain output, also the input buffer
is enabled
Else if PWM7 is routing to PV and PWM 7 is configured as PWM channel output, it will force the I/O state to be output
Else if PWM7 is routing to PV and PWM7 is configured as PWM emergency shutdown, it will force the I/O state to
be input
Else if SPI is routing to PV and SPI is enabled, SPI will determine the I/O state.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port V data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output
Else if corresponding TIM1 output compare channle is enabled, it will be force as output
Else if SPI is routing to PV and SPI is enabled, SPI will determined the I/O state
Else if PWM6 is routing to PV, it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-70. DDRV Register Field Descriptions
Description
Freescale Semiconductor