sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 266

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.4
7.4.1
The PLL is used to generate a high speed PLLCLK based on a low frequency REFCLK.
The REFCLK is by default the IRCCLK which is trimmed to f
If using the oscillator (OSCE=1) REFCLK will be based on OSCCLK. For increased flexibility, OSCCLK
can be divided in a range of 1 to 16 to generate the reference frequency REFCLK using the REFDIV[3:0]
bits. Based on the SYNDIV[5:0] bits the PLL generates the VCOCLK by multiplying the reference clock
by a 2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,
3, 4, 5, 6,... to 32 to generate the PLLCLK.
266
.
If oscillator is enabled (OSCE=1)
If oscillator is disabled (OSCE=0)
f VCO
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
If PLL is selected (PLLSEL=1)
Functional Description
=
Phase Locked Loop with Internal Filter (PLL)
2 f REF
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
SYNDIV
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
+
f PLL
f PLL
f bus
1
=
=
f REF
=
f REF
f PLL
------------- -
---------------------------------------- -
f VCO
--------------- -
POSTDIV
2
4
=
=
f VCO
------------------------------------ -
f IRC1M
REFDIV
NOTE
f OSC
+
1
+
1
IRC1M_TRIM
=1MHz.
Freescale Semiconductor