sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 381

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

10.4.1.11 General Call Address
To broadcast using a general call, a device must first generate the general call address($00), then after
receiving acknowledge, it must transmit data.
In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast
and receives data until the GCEN is disabled or the master device releases the bus or generates a new
transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the
address match.
In order to distinguish whether the address match is the normal address match or the general call address
match, IBDR should be read after the address byte has been received. If the data is $00, the match is
general call address match. The meaning of the general call address is always specified in the first data byte
and must be dealt with by S/W, the IIC hardware does not decode and process the first data byte.
When one byte transfer is done, the received data can be read from IBDR. The user can control the
procedure by enabling or disabling GCEN.
10.4.2
This is the basic mode of operation.
10.4.3
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate
normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module
enters a power conservation state during wait mode. In the later case, any transmission or reception in
progress stops at wait mode entry.
10.4.4
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC
register states.
10.5
The reset state of each individual bit is listed in
which details the registers and their bit-fields.
10.6
IICV3 uses only one interrupt vector.
Freescale Semiconductor
Interrupt
Resets
Interrupts
Operation in Run Mode
Operation in Wait Mode
Operation in Stop Mode
Offset
Vector
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Priority
Table 10-11. Interrupt Summary
Section 10.3, “Memory Map and Register
Source
Inter-Integrated Circuit (IICV3) Block Description
Description
Definition,”
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