sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 523

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

15.3.2.2
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Freescale Semiconductor
FDIVLCK
FDIV[5:0]
Field
5–0
6
Clock Divider Locked
0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
during Flash program and erase algorithms.
BUSCLK frequency. Please refer to
Flash Security Register (FSEC)
restore writability to the FDIV field.
1
2
BUSCLK is Greater Than this value.
BUSCLK is Less Than or Equal to this value.
BUSCLK Frequency
MIN
10.6
11.6
12.6
13.6
14.6
15.6
1.0
1.6
2.6
3.6
4.6
5.6
6.6
7.6
8.6
9.6
1
Table 15-7. FDIV values for various BUSCLK Frequencies
(MHz)
Table 15-6. FCLKDIV Field Descriptions (continued)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
MAX
10.6
11.6
12.6
13.6
14.6
15.6
16.6
1.6
2.6
3.6
4.6
5.6
6.6
7.6
8.6
9.6
2
FDIV[5:0]
Section 15.4.3, “Flash Command Operations,”
0x0C
0x0D
0x0A
0x0B
0x0E
0x0F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Table 15-7
Description
BUSCLK Frequency
MIN
16.6
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
26.6
27.6
28.6
29.6
30.6
31.6
shows recommended values for FDIV[5:0] based on the
1
(MHz)
MAX
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
26.6
27.6
28.6
29.6
30.6
31.6
32.6
32 KByte Flash Module (S12FTMRC32K1V1)
2
FDIV[5:0]
0x1C
0x1D
for more information.
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1E
0x1F
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