sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 367

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

The equation used to generate the divider values from the IBFD bits is:
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
Freescale Semiconductor
MUL=1
SCL
SDA
10-7. The equation used to generate the SDA Hold value from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
SDA
IBC[7:0]
SCL
(hex)
START condition
Table 10-7. IIC Divider and Hold Values (Sheet 1 of 6)
SCL Divider
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
(clocks)
Figure 10-5. SCL Divider and SDA Hold
SCL Hold(start)
SDA Hold
SCL Divider
(clocks)
Inter-Integrated Circuit (IICV3) Block Description
STOP condition
SCL Hold
(start)
SDA Hold
SCL Hold(stop)
SCL Hold
(stop)
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