sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 116

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1
1
Port Integration Module (S12HYPIMV1)
2.3.73
116
Function
Address 0x0290
In order TIM input capture to be function correctly, all the output function on the corresponding port shoud be set to 0. Also the
corresponding SRRU bit should be set to 0.
Read: Anytime.
Write: Anytime.
7,5,3,1
6,4,2,0
Altern.
Field
Field
PIFR
Reset
PTU
PTU
3-0
W
R
Port R interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSR register. To clear this flag, write logic level 1 to the corresponding bit in the PIFR register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
Port U general purpose input/output data—Data Register, Motor driver PWM output
Port U 7,5,3,1 pins are associated with the Motor PWM output.
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
Port U general purpose input/output data—Data Register, Motor driver PWM output, TIM0 channels 3-0
Port U 6,4,2,0 pins are associated with the Motor PWM output and TIM0 channels 3-0
When not used with the alternative functions, these pins can be used as general purpose I/O. If the associated data
direction bits of these pins are set to 1, a read returns the value of the port register, otherwise the buffered pin input
state is read.
M1C1P
• The Motor driver PWM takes precedence over the general purpose I/O function.
• The Motor driver PWM takes precedence over the TIM0 and the general purpose I/O function.
• The TIM0 output function takes precedence over the general purpose I/O function if related channel is enabled
PTU7
Port U Data Register (PTU)
—
0
7
IOC0_3
M1C1M
PTU6
0
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-61. PIFR Register Field Descriptions
Table 2-62. PTU Register Field Descriptions
Figure 2-71. Port U Data Register (PTU)
M1C0P
PTU5
—
0
5
M1C0M
IOC0_2
PTU4
0
4
Description
Description
M0C1P
PTU3
—
3
0
M0C1M
IOC0_1
PTU2
0
2
Freescale Semiconductor
M0C0P
Access: User read/write
PTU1
—
0
1
IOC0_0
M0C0M
PTU0
0
0
1
1