sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 151

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4
Interrupt Module (S12SINTV1)
4.1
The INT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to the CPU. The INT module supports:
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
4.1.1
Table 4-2
4.1.2
Freescale Semiconductor
Number
Version
01.01
01.02
01.03
•
•
•
•
•
•
•
I bit and X bit maskable interrupt requests
A non-maskable unimplemented op-code trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base
Introduction
contains terms and abbreviations used in the document.
Revision
13 Sep
21 Nov
13 Jun
Glossary
Features
2006
2007
2007
Date
Effective
Date
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Term
MCU
CCR
ISR
Author
Table 4-2. Terminology
Condition Code Register (in the CPU)
Interrupt Service Routine
Micro-Controller Unit
removed references to XIRQ/IRQ and added D2D error and D2D
interrupt instead
updates for S12P family devices:
- re-added XIRQ and IRQ references since this functionality is used
on devices without D2D
- added low voltage reset as possible source to the pin reset vector
added clarification of “Wake-up from STOP or WAIT by XIRQ with
X bit set” feature
Meaning
1
+ 0x0080).
Description of Changes
151