sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 308

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sc9s12hy64j0vllr

Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale’s Scalable Controller Area Network (S12MSCANV3)
9.1.1
9.1.2
308
Wake-Up Interrupt Req.
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Oscillator Clock
Glossary
Block Diagram
Bus Clock
oscillator clock
CAN clock
bus clock
CPU bus
CAN bus
FIFO
CAN
CRC
ACK
EOF
SOF
IFS
MSCAN
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Acknowledge of CAN message
Controller Area Network
Cyclic Redundancy Code
End of Frame
First-In-First-Out Memory
Inter-Frame Sequence
Start of Frame
CPU related read/write data bus
CAN protocol related serial bus
Direct clock from external oscillator
CPU bus realated clock
CAN protocol related clock
MUX
Figure 9-1. MSCAN Block Diagram
Configuration
CANCLK
Table 9-2. Terminology
Registers
Control
Status
and
Presc.
Tq Clk
Wake-Up
Low Pass Filter
Message
Buffering
Receive/
Transmit
Filtering
Engine
and
Freescale Semiconductor
RXCAN
TXCAN

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