sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 366

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Inter-Integrated Circuit (IICV3) Block Description
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
tap2tap column in
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
366
Table
IBC5-3
(bin)
000
001
010
011
100
101
110
111
10-5. The SCL Tap is used to generated the SCL period and the SDA Tap is used
Table
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
10-4, all subsequent tap points are separated by 2
Table 10-4. I-Bus Tap and Prescale Values
scl2start
Table 10-5. Prescale Divider Encoding
(clocks)
IBC2-0
(bin)
000
001
010
011
100
101
110
111
126
14
30
62
2
2
2
6
Table 10-6. Multiplier Factor
IBC7-6
00
01
10
11
scl2stop
SCL Tap
(clocks)
(clocks)
129
10
12
15
17
33
65
5
6
7
8
9
7
7
9
9
RESERVED
MUL
01
02
04
SDA Tap
(clocks)
(clocks)
scl2tap
126
14
30
62
1
1
2
2
3
3
4
4
4
4
6
6
(clocks)
tap2tap
IBC5-3
128
Table
16
32
64
1
2
4
8
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as shown in the
10-6.