sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 38

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Device Overview MC9S12HY/HA-Family
1.7.3
1.7.3.1
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the internal reference clock. XTAL is the oscillator output.
1.7.3.2
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a
known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an
internal pull-up device.
1.7.3.3
This input only pin is reserved for factory test. This pin has an internal pull-down device.
1.7.3.4
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has an internal pull-up device.
1.7.3.5
PAD[7:0] are a general-purpose input or output pins and analog inputs AN[7:0] of the analog-to-digital
converter ATD. They can be configured as keypad wakeup inputs.
1.7.3.6
PA[7:4] are a general-purpose input or output pins. They can be configured as frontplane segment driver
outputs FP[36:33].
1.7.3.7
PA[3:2] are a general-purpose input or output pins. They can be configured as frontplane segment driver
outputs FP[32:31]. PA3 can also be configure as API_EXTCLK.
1.7.3.8
PA1 is a general-purpose input or output pin. It can be configured as frontplane segment driver outputs
FP[30]. It also provide the non-maskable interrupt request input that provides a means of applying
asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ interrupt
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Detailed Signal Descriptions
EXTAL, XTAL — Oscillator Pins
RESET — External Reset Pin
TEST — Test Pin
BKGD / MODC — Background Debug and Mode Pin
PAD[7:0] / AN[7:0] / KWAD[7:0]— Port AD Input Pins of ATD [7:0]
PA[7:4] / FP[36:33]— Port A I/O Pins [7:4]
PA[3:2] / API_EXTCLK / FP[32:31]— Port A I/O Pins [3:2]
PA1 / XIRQ / FP[30]— Port A I/O Pin 1
The TEST pin must be tied to V
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
SSA
NOTE
in all applications.
Freescale Semiconductor