sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 476

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (S12SPIV5)
476
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
MSB first (LSBFE = 0):
t
t
t
t
MOSI pin
MISO pin
LSB first (LSBFE = 1):
L
T
I
L
Figure 13-12. SPI Clock Format 0 (CPHA = 0), with 8-bit Transfer Width selected (XFRW = 0)
, t
= Minimum idling time between transfers (minimum SS high time)
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
T
, and t
I
are guaranteed for the master mode and required for the slave mode.
t
L
MSB
LSB
1
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
2
Begin
Bit 6
Bit 1
3
4
Bit 5
Bit 2
5
6
Bit 4
Bit 3
7
Transfer
8
Bit 3
Bit 4
9
10
Bit 2
Bit 5
11
12
Bit 1
Bit 6
13 14
End
MSB
15
LSB
16
Minimum 1/2 SCK
Freescale Semiconductor
t
T
for t
Begin of Idle State
T
t
, t
I
l
, t
L
t
L