sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 118

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1
1
Port Integration Module (S12HYPIMV1)
2.3.76
2.3.77
118
Address 0x0293
Address 0x0294
Read: Always reads 0x00
Write: Unimplemented
Read: Anytime.
Write: Anytime.
PERU
Field
Reset
Reset
7-0
W
W
R
R
Port U pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
PERU7
PIM Reserved Registers
Port U Pull Device Enable Register (PERU)
0
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTU or PTIU registers, when changing the
DDRU register.
= Unimplemented or Reserved
PERU6
Figure 2-75. Port U Pull Device Enable Register (PERU)
0
0
0
6
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-65. PERU Register Field Descriptions
Figure 2-74. PIM Reserved Registers
PERU5
0
0
0
5
5
PERU4
NOTE
0
0
0
4
4
Description
u = Unaffected by reset
PERU3
3
0
0
3
0
PERU2
0
0
0
2
2
Freescale Semiconductor
PERU1
Access: User read/write
0
0
0
1
1
Access: User read
PERU0
0
0
0
0
0
1
1