sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 50

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Device Overview MC9S12HY/HA-Family
1.11.3.4
The RAM arrays are not initialized out of reset.
1.12
The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register at address 0x003C are
loaded from the Flash register FOPT. See
loaded from the Flash configuration field byte at global address 0x3_FF0E during the reset sequence.
1.13
The ATD module includes external trigger inputs ETRIG[3:0]. The external trigger allows the user to
synchronize ATD conversion to external trigger events.
trigger inputs.
50
COP Configuration
ATD External Trigger Input Connection
Memory
External Trigger
1. When LCD segment output driver is enabled on PP1/PP3, the ATD
2. Independent of the TIM0OCPD3/2 bit setting
external trigger function will be unavailable
ETRIG0
ETRIG1
ETRIG2
ETRIG3
Input
FOPT Register
FOPT Register
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
NV[2:0] in
Table 1-13. Initial COP Rate Configuration
Table 1-15. ATD External Trigger Sources
NV[3] in
Table 1-14. Initial WCOP Configuration
000
001
010
011
100
101
110
111
1
0
Table 1-13
TIM0 Channel output 2
TIM0 Channel output 3
and
Connectivity
Table 1-15
Table 1-14
COPCTL Register
COPCTL Register
PP1
PP3
CR[2:0] in
(1)
WCOP in
1
111
110
101
100
011
010
001
000
0
1
shows the connection of the external
for coding. The FOPT register is
(2)
2
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